Recently, high resolution TDCs have gained more and more interest due to their increasing implementation in digital PLLs, ADCs, jitter measurement and time-of-flight measurement units. Similar to ADCs, existing architectures of TDCs can be divided into several categories: flash TDCs [1,3], pipeline TDCs , and SAR TDCs . The highest achievable time resolution of a TDC is mainly limited by the CMOS gate delay. In order to get sub-gate-delay resolution, the Vernier method is commonly used. However, the mismatch problem caused by process variation limits its effectiveness, and the same holds for the time amplification method. The gated-ring-oscillator (GRO) method  is introduced to achieve sub-ps time resolution, but it still requires an equivalent CMOS gate delay as low as 6ps. Upcoming applications in 4th generation nuclear reactors, space and high energy physics like the Large Hadron Collider (LHC), require the TDC to achieve a high time resolution in harsh environments with high temperature and radiation, where the threshold voltage, transconductance, and delay of a transistor undergo dramatic changes. In these cases, the high accuracy and robustness of the TDC need to be inherent to the design rather than by employing a fast CMOS technology.
|Title of host publication||IEEE 2011 International Solid-State Circuits Conference Digest of Technical Papers|
|Place of Publication||United States|
|State||Published - 24 Feb 2011|
|Event||ISSCC 2011 - International Solid State Circuits Conference - IEEE, San-Francisco|
Duration: 20 Feb 2011 → 24 Feb 2011
|Conference||ISSCC 2011 - International Solid State Circuits Conference|
|Period||2011-02-20 → 2011-02-24|