Electrical Performance and Reliability Aspects of Strain Engineered Deep Submicron CMOS Technologies

To keep track with Moore’s law, strain engineering based on either a global or a local approach is gaining much interest and has already been successfully implemented for 65 and 45 nm technology nodes. Although the first goal is to improve the drive current by mobility enhancement, other performance parameters such as leakage current, carrier lifetime and low frequency 1/f noise have to be considered. The implementation of stressors also impacts the radiation hardness of the devices. First some general comments are given on strain engineering techniques already used, before discussing more in detail their impact on several electrical device parameters. Attention mainly will be given to illustrate a global approach based on strained Si on strain-relaxed SiGe buffer layers and the use of process-induced stressors such as an embedded SiGe layer and a contact etch stop layer (CESL). Both are gaining strong interest for implementation in a FinFET technology. Some advantages and disadvantages of the different approaches will be outlined.