Over the last 20 years, analog and digital communication systems have evolved enormously. Driven by the aggressive scaling policy in the digital systems and micro-processors market, wireless communications systems, once multi-chip systems with a strict separation between analog and digital signal processing have evolved into complete systems on chip (SoC). The presented research fits into the ever continuing quest for cheaper, smaller, completer and hence more complicated integrated circuits. The ultimate goal being the single chip solution, a monolithic integration, removing as much external components as possible is targeted. Due to its low cost, low power and mixed signal potential, Si CMOS is the technology of choice in this work. This work discusses one of the key building blocks for this kind of electronic systems, the frequency synthesizer. Within the numerous architectures available to implement a frequency synthesizer, this work focuses on the phase locked loop (PLL) due to its superior spectral performance compared to other implementation styles. Low phase noise and low spurious tones will allow higher quality information transfer. This dissertation is conceived as a step by step guide towards the design of a monolithic phase locked loop (PLL) implemented in a standard CMOS process.
|Place of Publication||Leuven, Belgium|
|State||Published - Apr 2008|